1. Field of the Invention
The present invention relates to the field of 3D semiconductor packaging, and, more particularly, to techniques and structures used to facilitate testing of conductive vias.
2. Description of the Related Art
In stacked-chip packaging, multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure. Use of through silicon vias (TSV) has been a key technology in realizing stacked-chip packaging integration due to the ability to provide short vertical conductive paths between chips.
Conventionally, in the TSV manufacturing process, a semiconductor wafer is etched from its bottom surface to form a plurality of via holes such that a bottommost patterned metal layer (i.e., “metal one” (M1)) of the semiconductor wafer is exposed. Then, the via holes are plated with a conductive metal so as to form the through silicon vias (TSVs). The semiconductor wafer is then sawed to form semiconductor dice. In some cases, during the etching process of the semiconductor wafer, the etchant may not etch the semiconductor wafer precisely, so that some via holes will not reach to the bottommost patterned metal layer (M1). In other cases, during the plating process of the conductive metal, the plating parameter may not be controlled well, so that the thickness of the conductive metal is not even, and some conductive metal will not contact the bottommost patterned metal layer (M1). The above two cases will result in that the conductive metal of the TSV will not stop on the bottommost patterned metal layer (M1) perfectly in the plating process, and an open circuit is formed between the conductive metal and the bottommost patterned metal layer (M1). However, such undesired defects are found only upon performing a test on the semiconductor die, which means such undesired defects are found only after the semiconductor wafer had been sawed into the semiconductor dice.